1. Field of the Disclosure
The present disclosure relates generally to an electronic apparatus, processor, and a control method thereof, and more particularly, to an electronic apparatus for scheduling and processing received instructions and data, a processor, and a control method thereof.
2. Description of the Related Art
Processors, such as very long instruction word (VLIW) and coarse-grained array (CGA) processors, schedule a plurality of instructions simultaneously to raise instruction level parallelism (ILP). In such a processor, each instruction is separated into pipeline stages, such as fetch, decode, execution, and write back, in a function unit (FU) that supports the instruction and is executed continuously.
A compiler checks dependencies and resources between instructions to perform scheduling. The compiler determines whether the input ports and output ports of an FU, such as an issue or a write back, are occupied per cycle. That is, the compiler checks for a port conflict and performs scheduling.
For example, if a multiplication instruction of latency 2 is input in a first cycle, output data is output in a third cycle. When an addition instruction of latency 1 is input in a second cycle, output data is output in the third cycle, and a collision occurs at the output port. Thus, an addition instruction cannot be issued in the second cycle. In this case, if there is no dependency between the multiplication instruction and the addition instruction, the addition instruction may be discussed first, but if the scheduling order is changed, the scheduling algorithm becomes complicated. Generally, the addition instruction is issued in the third cycle.
In particular, if instructions with long latency are issued consecutively, the probability of port conflict increases and the scheduling efficiency deteriorates. Accordingly, there is a need for improved scheduling efficiency, without causing port conflicts.